1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor, and more particularly to a semiconductor device including a low dielectric constant film and a manufacturing method therefor.
2. Background Art
In recent years, an increasing number of semiconductor devices have employed a multilayer wiring structure to achieve miniaturization and high speed operation. However, this has raised the problem of signal delay due to an increase in the wiring resistance and in the parasitic capacitance between the wires and between the wiring layers. Signal delay T is proportional to the product of wiring resistance R and parasitic capacitance C. Therefore, reducing the signal delay T requires reducing the parasitic capacitance as well as reducing the resistance of the wiring layers.
Low resistance wiring material may be used to reduce the wiring resistance R. Specifically, copper (Cu) wiring may be used instead of the conventional aluminum (Al) wiring.
The parasitic capacitance between two wiring layers is related to the relative dielectric constant of the interlayer insulating film provided between the wiring layers by the equation: C=(e·S)/d, where C is the parasitic capacitance, e is the relative dielectric constant, S is the side area of the wiring layers, and d is the distance between the wiring layers. Therefore, reducing the parasitic capacitance C requires reducing the dielectric constant of the interlayer insulating film. To achieve this, efforts are being made to develop and use an insulating film having lower relative dielectric constant than conventional SiO2 films (having a relative dielectric constant of 3.9) as the interlayer insulating film. (Such a low dielectric constant insulating film is hereinafter referred to as “Low-k film”.) Especially, organic siloxane insulating films are attracting attention since they can achieve a relative dielectric constant of 3.1 or less.
An organic siloxane insulating film can be formed by the chemical vapor deposition method (hereinafter referred to as “CVD method”) or a spin coat method. In either way, the formed organic siloxane insulating film has a structure made up of a network formed of Si—O—Si bonds and Si—R (R: an organic group) bond side chains. It should be noted that CH3, which has good heat resistance, is typically used as R. The organic siloxane insulating film may include Si—H bonds or Si—C—Si bonds as other components. Further, unreacted substances or reaction byproducts including C may remain within the insulating film as impurities.
A typical CVD method for forming an organic siloxane insulating film uses organic silane and oxidizing gas. Another known method uses an alkoxysilane such as R2Si(OR′)2 or R4Si2O(OR′)2 (where R and R′ each represent CH3) and an inert gas and forms the film by retaining the material gas within the reaction chamber under long residence time condition (see, e.g., Patent Document 1). The organic siloxane insulating films formed by these methods generally have a hardness of 2 GPa or less.
Still another known method uses another type of alkoxysilane, namely RnSi(OR′)3-n (where: R represents CH3; R′ represents CH3 or C2H5; and 0.75≦n≦1.5). This method mixes the alkoxysilane with an inert gas and forms an organic siloxane insulating film by retaining the material gas within the reaction chamber under short residence time condition (see, e.g., Patent Document 2). The organic siloxane insulating film produced by this method has a hardness of 4.4 GPa and a ratio of carbon atoms to silicon atoms between 1 and 2, inclusive, that is, 1≦(C/Si)≦2.
On the other hand, organic siloxane insulating films produced by the spin coat method are known to have a relative dielectric constant of 3 or less and a Young's modulus of less than 50 GPa (see, e.g., Patent Document 3). In this case, a protective film having a Young's modulus of 50 GPa or more must be laminated onto the organic siloxane insulating film to protect the insulating film from mechanical damage during wire bonding.
Incidentally, a known method for forming copper wiring by using a Low-k film employs a damascene technique. This technique forms copper wiring without etching the copper, since the etching of copper is more difficult to control than that of aluminum.
Specifically, the damascene technique performs the following steps: forming an SiO2 film on the Low-k film; dry-etching these films using a resist pattern as a mask to form an opening; and forming a barrier metal film on the opening and filling the opening with a copper layer to form a copper wiring layer. Specifically, after forming the copper layer by use of a plating technique such that the opening is buried under the copper layer, the surface is polished by the chemical mechanical polishing method (hereinafter referred to as “CMP method”) such that the copper layer remains only within the opening.    [Patent Document 1]
Japanese Laid-Open Patent Publication No. 2000-349083    [Patent Document 2]
Japanese Laid-Open Patent Publication No. 2001-203200    [Patent Document 3]
Japanese Laid-Open Patent Publication No. 2000-340569
When an organic siloxane insulating film is used as the Low-k film, the CMP process polishes off (or removes) the entire SiO2 film and part of the organic siloxane insulating film to ensure flatness of the surface. After that, a plasma treatment is carried out to reduce the surface of the copper layer and clean the surface of the organic siloxane insulating film. Then, a barrier insulating film is formed on the surfaces of the copper layer and the organic siloxane insulating film to prevent diffusion of copper. However, the above reducing plasma treatment process has a problem in that a layer with altered properties (referred to hereinafter as “an altered layer”) is formed on the surface of the organic siloxane insulating film due to reduction of carbon within the organic siloxane insulating film.
The altered layer has poorer electrical characteristics than the original insulating layer, resulting in a degradation in the insulation characteristics between the adjoining layers. This problem worsens with decreasing wiring distance.
To address this problem, an SiO2 film may be deposited on the organic siloxane insulating film to a large thickness (approximately 100 nm) and the above CMP method may be carried out such that the surface of the SiO2 film is exposed after the polishing, instead of the organic siloxane insulating film. Since the SiO2 film contains substantially no carbon, this method can prevent formation of an altered layer due to the reducing plasma treatment. However, the SiO2 film has a high relative dielectric constant, which prevents the effective parasitic capacitance C between wires from being reduced.
Further, the above degradation of the electrical characteristics is dependent on the thickness of the altered layer; the thinner the thickness of the layer, the better the electrical characteristics. To reduce the thickness of the altered layer, the reducing plasma treatment time may be reduced. However, this leads to insufficient reduction of the copper layer surface and insufficient cleaning of the insulating film surface, which is not desirable.
Use of an insulating film of the type in which the above altered layer is hardly formed eliminates the need for forming an SiO2 film on the insulating film. For example, the above insulating film formed of RnSi(OR′)3-n is of such type. However, since this film contains a very large amount of carbon, a sufficient etching selectivity ratio cannot be ensured during dry-etching the film using a resist pattern as a mask.